The present invention relates to a method for fabricating a bipolar transistor, and more particularly relates to a method for fabricating a bipolar transistor in which epitaxial growth is not used.
In recent years, as the cellular phone market and the mobile equipment market have been expanding, reduction in costs for bipolar transistors as a high-speed operation device has been required. Hereinafter, a known method for fabricating a bipolar transistor will be described with reference to the accompanying drawings.
First, a method for fabricating a bipolar transistor according to a first known example will be described with reference to FIGS. 7A through 7E (see, e.g., Japanese Examined Patent Publication No. 59-50227).
FIGS. 7A through 7E are cross-sectional views illustrating respective steps of a method for fabricating a bipolar transistor according to the first known example.
First, as shown in FIG. 7A, a p-type semiconductor single crystalline substrate 500 made of silicon and doped with boron at a concentration of 1xc3x971015 atoms/cm3 is prepared.
Next, as shown in FIG. 7B, using a mask (not shown) having an opening portion corresponding to a buried-collector-layer-forming region, arsenic ions are implanted into the semiconductor single crystalline substrate 500 at an injection dose of 5xc3x971015 atoms/cm2. An injection angle in this ion implantation process is slightly tilted (by about 7 degree) from the normal direction of the semiconductor single crystalline substrate 500. By the ion implantation process, a buried collector layer 501 is formed in a predetermined region of the semiconductor single crystalline substrate 500. Thereafter, an epitaxial layer 502 which is doped with phosphorus at a concentration of about 1xc3x971016 atoms/cm3 and has a thickness of about 1 xcexcm is formed over the semiconductor single crystalline substrate 500. Note that after the epitaxial layer 502 has been formed, arsenic ions introduced into the buried collector layer 501 are diffused in a lower potion of the epitaxial layer 502, so that the buried collector layer 501 expands.
Next, as shown in FIG. 7C, using a mask (not shown) having an opening portion through which a collector-wall-forming region of the epitaxial layer 502 is exposed, phosphorus ions are implanted into the semiconductor single crystalline substrate 500 at an injection dose of 2xc3x971015 atoms/cm2, thereby forming a collector wall layer 503 in a predetermined region of the epitaxial layer 502. Thereafter, thermal treatment at a temperature of 1000xc2x0 C. is performed to the semiconductor single crystalline substrate 500 for 30 minutes, thereby expanding the collector wall layer 503 so that the collector wall layer 503 has a thickness enough to reach the buried collector layer 501.
Next, as shown in FIG. 7D, using a mask (not shown) having an opening portion through which a base-layer-forming region of the epitaxial layer 502 is exposed, boron ions are implanted into a surface portion of the epitaxial layer 502 at an injection dose of 3xc3x971013 atoms/cm2, thereby forming a base layer 504 in a predetermined region of the surface portion of the epitaxial layer 502. Then, using a mask (not shown) having an opening portion through which an emitter-layer-forming region of the base layer 504 is exposed, arsenic ions are implanted into the semiconductor single crystalline substrate 500 at an injection dose of 4xc3x971015 atoms/cm2, thereby forming an emitter layer 505 in a predetermined region of a surface portion of the base layer 504. Thereafter, thermal treatment at a temperature of 850xc2x0 C. is performed to the semiconductor single crystalline substrate 500 for about 30 minutes, thereby activating impurities introduced into the base layer 504 and the emitter layer 505, respectively.
Next, as shown in FIG. 7E, an oxide film 506 made of a BPSG (borophosphosilicate glass) film having a thickness of about 1 xcexcm is deposited over the semiconductor single crystalline substrate 500 using CVD (chemical vapor deposition) to protect a surface of a bipolar transistor including the epitaxial layer 502, the base layer 504, the emitter layer 505 and the like. Thereafter, a collector electrode 507, a base electrode 508 and an emitter electrode 509 (i.e., electrodes of a bipolar transistor) connected to the collector wall layer 503, the base layer 504 and the emitter layer 505, respectively, and made of aluminum are formed by sputtering. Thus, a bipolar transistor is completed. Note that although not shown in FIGS. 7A through 7E, the elemental bipolar transistor described above is surrounded using an appropriate isolation technique, for example, by a dielectric isolation region or a PN junction isolation region, so as to be electrically isolated from other semiconductor elements to be formed in the periphery of the elemental bipolar transistor.
Next, a method for fabricating a bipolar transistor according to a second known example will be described with reference to FIGS. 8A through 8E (see, e.g., Japanese Unexamined Patent Publication No. 2001-291781).
FIGS. 8A through 8E are cross-sectional views illustrating respective steps of a method for fabricating a bipolar transistor according to the second known example. Note that in FIGS. 8A through 8E, the same members as those described in the first known example are identified by the same reference numerals.
As shown in FIG. 8A, a p-type semiconductor single crystalline substrate 500 made of silicon and doped with boron at a concentration of 1xc3x971015 atoms/cm3 is prepared.
Next, as shown in FIG. 8B, using a mask (not shown) having an opening portion corresponding to a collector-layer-forming region, phosphorus ions are implanted into the semiconductor single crystalline substrate 500 at a dose of 5xc3x971012 atoms/cm2. An injection angle in this ion implantation process is slightly tilted (by about 7 degree) from the normal direction of the semiconductor single crystalline substrate 500. By this ion implantation process, a collector layer 510 is formed in a predetermined region of the semiconductor single crystalline substrate 500.
Next, as shown in FIG. 8C, thermal treatment at a temperature of 1100xc2x0 C. is performed to the semiconductor single crystalline substrate 500 for 100 minutes, thereby activating the collector layer 510 while expanding the collector layer 510 to a predetermined depth.
Thereafter, process steps shown in FIGS. 8D and 8E are performed. The process steps are the same as those of FIGS. 7C through 7E used for the first known example.
In the method for fabricating a bipolar transistor according to the first known example, the epitaxial layer 502 is formed. Therefore, fabrication costs are increased. Moreover, because of the existence of the epitaxial layer 502 which is unique to the bipolar transistor, properties of an MOS transistor vary if one or more fabrication process steps for fabricating a bipolar transistor are added to existing CMOS (complementary metal oxide semiconductor) processes.
Moreover, in the second known example, a collector layer 510 is formed using an n-type well, instead of an epitaxial layer. In this case, to ensure the breakdown voltage of a bipolar transistor, the collector layer 510 has to be formed at a great depth in the downward direction from a surface of the semiconductor single crystalline substrate 500. Therefore, drive-in diffusion at a high temperature is normally performed. However, an impurity introduced through ion implantation is diffused not only in the downward direction but also in the lateral direction. Therefore, taking it into consideration that the collector layer 510 (see FIG. 8B) formed on the surface portion of the semiconductor single crystalline substrate 500 through ion implantation expands also in the lateral direction (see FIG. 8C) due to a high temperature drive-in diffusion, a clearance between adjacent collector layers 510 for bipolar transistors has to be increased. Accordingly, a problem arises in which the area of a final device is increased.
By the way, as means for solving the above-described problems, a method in which an impurity doped layer, such as an epitaxial layer, having a uniform impurity profile is formed, i.e., multiple ion implantation (see, e.g., D. H. Lee, J. W. Mayer, xe2x80x9cIon-Implanted Semiconductor Devicexe2x80x9d, Proceeding of the IEEE, Vol. 62, No. 9, pp. 1241-1255, USA, 1972) has been known.
However, multiple ion implantation has the following problem.
FIG. 9 is a graph showing an impurity profile obtained by multiple ion implantation, and more specifically, the relationship between a depth from a surface of semiconductor single crystalline substrate (hereinafter, referred to as a xe2x80x9csubstrate surfacexe2x80x9d) which an injected impurity reaches and the concentration of the injected impurity.
As shown in FIG. 9, multiple ion implantation is a method in which while ion implantation processes at different injection energies are repeated to subsequently create impurity profiles with intermittently different peak positions (depth from the substrate surface in FIG. 9) of an impurity concentration, and also these impurity profiles are summed up to obtain an impurity profile having a substantially uniform impurity concentration.
If such multiple ion implantation is used, it is possible to create an impurity profile which corresponds to an epitaxial layer and in which the distribution of the impurity concentration is constant in the semiconductor single crystalline substrate thickness direction. However, in multiple ion implantation, ion implantation with multiple steps has to be performed under different injection conditions (acceleration energy level), and thus the number of ion implantation processes is increased. Accordingly, damages accumulated in a semiconductor single crystalline substrate are increased, causing deterioration of device properties. Moreover, multiple ion implantation has another problem in which because the number of ion implantations is large, processing time is increased, thus resulting in increase in fabrication costs.
In view of the above-described problems, it is an object of the present invention to allow fabrication of a bipolar transistor without performing an epitaxial growth process while avoiding adverse effects caused by multiple ion implantation.
A method for fabricating a bipolar transistor according to the present invention includes: a first step of implanting, along the normal direction of the principle surface of a first-conductive-type semiconductor single crystalline substrate, ions of a second-conductive-type first impurity into the semiconductor single crystalline substrate to form a second-conductive-type collector layer; a second step of implanting, along a direction tilted from the normal direction, ions of a second-conductive-type second impurity into the semiconductor single crystalline substrate at a higher injection energy than that in the ion implantation of the first step to form a second-conductive-type buried collector layer in a lower portion of the collector layer; and a third step of forming each of a first-conductive-type base layer and a second-conductive-type emitter layer in a predetermined region of a surface portion of the collector layer.
According to the inventive method for fabricating a bipolar transistor, along the normal direction of the principle surface of a first-conductive-type semiconductor single crystalline substrate (hereinafter, referred to as a xe2x80x9csubstrate surfacexe2x80x9d), ions of a second-conductive-type first impurity are implanted into the semiconductor single crystalline substrate to form a second-conductive-type collector layer. In this case, atoms (semiconductor atoms) constituting the semiconductor single crystalline substrate array, thereby forming crystalline lattices. Thus, the injected first impurity does not stay in a surface portion of the semiconductor single crystalline substrate (hereinafter, referred to as a xe2x80x9csubstrate surface portionxe2x80x9d) but travels in the semiconductor single crystalline substrate. Specifically, the first impurity passes through between crystalline lattices to reach a deeper portion of the substrate than the substrate surface. (This is so called channeling phenomenon. Note that although a current path formed directly under a gate electrode of an MOS device is referred to as a xe2x80x9cchannelxe2x80x9d. However, needless to say, this channel has a different concept from that of the channel used in the present application.) As a result, a collector layer having an impurity profile with a constant distribution of the concentration of the first impurity in the thickness direction of the semiconductor single crystalline substrate is formed. Thus, a similar impurity profile to that of a known epitaxial layer can be obtained by a single ion implantation process. Accordingly, accumulation of damages in a semiconductor single crystalline substrate due to ion implantation, which has been a problem of the known multiple ion implantation in which multiple ion implantation processes are separately preformed in different stages can be prevented. Moreover, increase in fabrication costs can be avoided.
In contrast, in the second step of forming a second-conductive-type buried collector layer, ions of a second impurity are implanted into the semiconductor single crystalline substrate along a direction tilted from the normal direction of the substrate surface. Ions of the second impurity implanted by the ion implantation from such a tilted direction tend to collide with semiconductor atoms which regularly array when traveling in the semiconductor single crystalline substrate. Therefore, in the second step, ions of the second impurity are concentratedly implanted at a predetermined depth so that an impurity profile in which a sharp peak of the concentration of the second impurity is located at the predetermined depth from the substrate surface. Furthermore, when the ion implantation of the second impurity is performed at a higher injection energy than that in the ion implantation of the first impurity, ions of the second impurity can be implanted at a deeper position of the substrate than the substrate surface according to an injection energy level. Thus, a buried collector layer having an impurity profile with a sharp concentration peak can be formed in a lower portion of the collector layer. Therefore, a bipolar transistor having a similar impurity profile to that of a known bipolar transistor including a buried collector layer and an epitaxial layer can be fabricated by the ion implantations of the first and second impurities. That is to say, an epitaxial growth process can be omitted from fabrication process steps for fabricating a bipolar transistor.
Moreover, in the known method, a buried collector layer has to be formed before an epitaxial layer is formed. However, according to the present invention, ion implantation is performed at a high injection energy. Thus, even after a collector layer (corresponding to the known epitaxial layer) has been formed, a buried collector layer can be selectively formed in a lower portion of the collector layer.
Moreover, according to the inventive method for fabricating a bipolar transistor, the same mask can be used to form a collector layer and a buried collector layer. Therefore, fabrication costs can be suppressed to a low level.
In the inventive method for fabricating a bipolar transistor, it is preferable that an injection dose in the ion implantation of the second step is 10 times or more as much as that in the ion implantation of the first step, and an injection energy in the ion implantation of the second step is 6 time or more as much as that in the ion implantation of the first step.
Thus, a buried collector layer into which the second-conductive-type second impurity is introduced at a high concentration can be reliably formed in a lower portion of the collector layer. Therefore, it is possible to reliably form a bipolar transistor having a similar impurity profile to that of an epitaxial layer formed through epitaxial growth.
In the inventive method for fabricating a bipolar transistor, it is preferable that the third step includes forming the base layer in a predetermined region of the surface portion of the collector layer, forming, on the semiconductor single crystalline substrate in which the base layer is formed, a mask having a first opening portion through which an emitter-layer-forming region of the base layer is exposed and a second opening portion through which a collector-contact-layer forming region is exposed, and forming, using the mask, the emitter layer in part of the base layer located under the first opening portion simultaneously with a second-conductive-type collector contact layer in part of the collector layer located under the second opening portion.
Thus, a second-conductive-type collector contact layer is formed in a predetermined region of a surface portion of the collector layer. Accordingly, with the collector contact layer connected to the collector electrode, contact resistance generated in a connection portion of the collector layer and the collector electrode can be reduced. Therefore, the current driving ability of the bipolar transistor can be improved. Moreover, a mask for forming the emitter layer is used to form the collector contact layer. Thus, a process step for forming a collector contact layer is not necessarily added. Therefore, it is possible to fabricate a high performance bipolar transistor while achieving cost maintenance.
Furthermore, it is preferable that the collect contact layer is formed so as to surround the base layer.
Thus, a second-conductive-type collector contact layer is formed in a region of the surface portion of the collector layer located between the semiconductor single crystalline substrate and the base layer. That is to say, the collector contact layer is formed so as to surround the base layer. Therefore, the second-conductive-type impurity can be supplied to the region of the surface portion of the collector layer in which the collector layer is formed. In other words, the second-conductive-type collector contact layer can be reliably provided in a region of the surface portion of the collector layer located between the semiconductor single crystalline substrate and the base layer. It is because the channeling phenomenon occurs in the surface portion of the collector layer when ion implantation is performed why the second-conductive-type impurity is supplied in this manner. There may be cases where if the channeling phenomenon occurs, the concentration of the second-conductive-type impurity is reduced in the surface portion. However, when the collector contact layer is formed in the above-described manner, the concentration of the second-conductive-type impurity in the surface portion of the collector layer is reduced. Thus, for example, deterioration of the punch through breakdown voltage between a first-conductive-type semiconductor single crystalline substrate and a first-conductive-type base layer can be prevented. Moreover, inversion of the conductive type of the surface portion of the collector layer due to influence of a voltage applied to an interconnect can be prevented.
It is preferable that the inventive method for fabricating a bipolar transistor further includes between the second and third steps, the step of implanting ions of a second-conductive-type third impurity into the semiconductor single crystalline substrate to form a second-conductive-type inversion preventing layer in the surface portion of the collector layer, an injection dose in the ion implantation of the step of forming an inversion preventing layer is smaller than that in the ion implantation of the first step, and an injection energy in the ion implantation of the step of forming an inversion preventing layer is smaller than that in the ion implantation of the first step.
Thus, ion implantation of the third impurity is performed at a lower injection energy than that of the ion implantation of the first impurity, so that an inversion preventing layer of the same conductive type as that of the collector layer, i.e., the second-conductive-type is formed in the surface portion of the collector layer formed in the semiconductor single crystalline substrate. Accordingly, even if the concentration of the second-conductive-type first impurity in the surface portion of the collector layer is reduced due to the above-described channeling phenomenon caused when ion implantation is performed, it is possible to supply the second-conductive-type third impurity to the surface portion of the collector layer. Therefore, as described above, deterioration of the punch through breakdown voltage due to reduction of the concentration of the first impurity in the surface portion of the collector layer or inversion of the conductive type of the surface portion of the collector layer into the first conductive type can be prevented.
Moreover, a plurality of doped layers (i.e., collector layer, buried collector layer and inversion preventing layer) can be formed using the same mask, so that fabrication costs can be suppressed to a low level and also an inversion layer can be formed without causing any location gap between a region of the substrate surface portion in which a collector layer is to be formed and a region of the substrate surface portion in which an inversion preventing layer is to be formed.
In the inventive method for fabricating a bipolar transistor, it is preferable that after the third step, thermal treatment is performed to the semiconductor single crystalline substrate to activate the collector layer, the buried collector layer, the base layer, and the emitter layer.
Thus, it is sufficient to perform thermal treatment at a low temperature for activating injected impurities, so that high temperature thermal treatment such as thermal treatment required in drive-in diffusion shown in the first and second known examples is not necessary. Therefore, expansion of each of the doped layers in the lateral direction can be prevented, thus suppressing increase in a device area.